1. Field of Use
This invention relates to memory systems containing semiconductor memory elements including those in which stored information must be periodically refreshed to preserve the integrity of such information.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in the copending patent application "System Providing Multiple Fetch Bus Cycle Operation", invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., Ser. No. 867,270, filed on Jan. 5, 1978 now U.S. Pat. No. 4,236,203, issued on Nov. 25, 1980 and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a series of response cycles. While this arrangement improves the system throughput capabilities, it becomes desirable to be able to provide access to both words simultaneously over a single bus.
It will be noted that in such paired memory module systems, it is necessary to generate and decode even and odd addresses for accessing both memory modules. Such an arrangement for accomplishing the generation/decoding is described in copending patent application "A Dynamic Memory System which Includes Apparatus for Performing Refresh Operations in Parallel with Normal Memory Operations", invented by Robert B. Johnson and Chester M. Nibby, Jr., Ser. No. 926,480, filed on July 20, 1978 now U.S. Pat. No. 4,185,323, issued on Jan. 22, 1980 and assigned to the same assignee as named herein.
In the above arrangement, the low order bits of the address provided with the memory request specify the storage location being accessed while the high order bits specify which row of RAM chips is being selected. In order to fetch the second word of the pair being accessed, it is necessary to increment by one the memory request address and then decode the incremented address. This results in additional delay in generating the required address increasing the overall time in delivering the requested word pair to the bus. Moreover, it also necessitates additional counter or incrementing circuits.
Accordingly, it is an object of the present invention to provide a memory system which provides for read out of a plurality of words from a corresponding number of memory modules with minimum delay.
It is a further object of the present invention to provide a method and apparatus which minimizes the circuitry and delay for providing at least a pair of words from a memory system which couples to a multiword bus.